1. Field of the Invention
The present invention relates to a QDPSK (Quad Differential Phase Shift Keying) demodulating circuit in accordance with the Costas loop method, and in particular to an improvement in a phase-error detecting circuit for a demodulating circuit.
2. Description of the Related Art
QDPSK is a formality of phase modulation in which the instantaneous phase of the subcarrier is shifted by 0, 90.degree., 180.degree. or 270.degree. corresponding to the 2 bit PCM code. Data transmission in accordance with the QDPSK, as is commonly known, has the advantage that demodulation can be effected without knowing the absolute phase of the standard-phase signal generated in the transmitter end. This causes, however, the necessity to regenerate the standard-phase signal in the receiver end. The Costas loop method provides a useful tool for regenerating the standard-phase signal.
A brief explanation will be given below on the Costas loop method with reference to the technical paper entitled "Principle of Operation of IC .mu.PC1478C adapted for QDPSK Demodulation in a Receiver for Satellite Broadcasting" on pages 917 through 924 of Data Book, Catalogue Number MA-102B, issued by NEC CORP. in December 1989.
FIG. 1 shows a schematic diagram of a QDPSK demodulating circuit. The demodulating circuit is made up of phase demodulators 12 and 14, phase-error detecting circuit 16, low-pass filter (LPF) 18, voltage-controlled oscillator (VCO) 19 and phase shifter 20. QPSK signal S is supplied to phase demodulators 12 and 14 through input terminals 11. Each of phase demodulators 12 and 14 is provided with a multiplier and an LPF. The multiplier generates the product of signal S and regeneration signal L.sub.P or L.sub.Q, where regeneration signal L.sub.P is fed from VCO 19 directly to phase demodulator 12 and regeneration signal L.sub.Q is fed through .pi./4 phase shifter 20 to phase demodulator 14. The LPF cuts off the high frequency component contained in the product signal, thus delivering demodulated signal P or Q.
Now, if EQU S=Ecos (.omega.t+.theta.) (1) EQU L.sub.P =E.sub.1 sin (.omega.t+.theta..sub.1) (2)
and EQU L.sub.Q =E.sub.1 cos (.omega.t+.theta..sub.1), (3)
where .theta. takes values 2n.pi./4 (n=0, 1, 2, ...) corresponding to the PCM code to be transmitted, the standard-phase signal being Ecost .omega.t, then it follows that EQU S.times.L.sub.P= 2.sup.-1 EE.sub.1 { cos(2.omega.t+.theta.+.theta..sub.1) sin (.theta..sub.1-.theta.)}. (4)
Since the first term on the right side of equation (4) is cut off by the LPF in phase demodulator 12, it follows that EQU P=2.sup.-1 EE.sub.1 sin (.theta.-.theta..sub.1). (5)
Similarly, EQU Q=2.sup.-1 EE.sub.1 cos (.theta.-.theta..sub.1). (6)
Phase-error detecting circuit 16, receiving demodulated signals P and Q, computes (P.sup.2 -Q.sup.2) PQ and delivers the computation as phase error signal R. For this end, phase-error detecting circuit 16 is provided with multiplying circuit 161 to produce P.times.Q, adding circuit 162 to produce P+Q, subtracting circuit 163 to produce P-Q, multiplying circuit 164 to produce P.sup.2 -Q.sup.2 from the outputs of adding and subtracting circuits 162, 163 and multiplying circuit 165 to produce R=(P.sup.2 -Q.sup.2) PQ from the outputs of multiplying circuits 161 and 164.
It follows from equations (5) and (6) that ##EQU1##
Accordingly, if .theta.-.theta..sub.i takes any value of n.pi./4 (n=0, 1, 2, ...), then the QDPSK demodulating circuit is phase-locked. Conversely, if the ODPSK demodulating circuit is phase-locked for any input QPSK signal S, the QPSK signal is a signal which has a phase shifted by n.pi./4 radian with respect to a phase of the signal generated by VCO 19. Accordingly, the output signal of VCO 19 will be coherent, or phase-synchronized with the standard-phase signal when the QDPSK demodulating circuit is phase-locked. In this way, the standard-phase signal is regenerated in the receiver end.
The above is an outline of a QDPSK demodulating circuit according to the Costas loop method. FIG. 2 shows a typical phase-error detecting circuit of the prior art, and FIG. 3 shows a block diagram of the quartic multiplier shown in FIG. 2.
The phase-error detecting circuit of FIG. 2 consists of two parts. The first part is a biquadratic multiplier made up of serially connected four-stage differential amplifiers. Hereafter, a differential amplifier made up of transistors Q1, Q2 is referred to as differential amplifier (Q1, Q2), and a differential amplifier made up of double differential amplifiers (Q1, Q2) and (Q3, Q4) is referred to as differential amplifier (Q1, Q2; Q3, Q4). The 1st stage differential amplifier (Q11, Q12) supplied with demodulated signal P and constant voltage V1 generates an output current signal proportional to P-V1. Hereafter the current signal proportional to P-V1 is referred to as current signal P. Current signal P drives the emitters of 2nd stage differential amplifier (Q13, Q14; Q15, Q16). Since differential amplifier (Q13, Q14; Q15, Q16) is supplied with demodulated signal Q and constant voltage V2, the cross-coupled collectors of differential amplifier (Q13, Q14; Q15, Q16) carries an output current signal proportional to (P-V1)(Q-V2). Hereafter the current signal proportional to Q-V2 is referred to as current signal Q. Thus, serially connected two-stage differential amplifiers (Q11, Q12) and (Q13, Q14; Q15, Q16) constitute multiplying circuit 161 shown in FIGS. 1 and 3, which provides current output P.times.Q. This type of multiplier will be referred to as the multiplication demodulator type, because it is often used to demodulate a double-balanced modulated signal. Differential amplifier (Q17, Q18; Q19, Q20), receiving signals P.sub.1 and Q.sub.1, provides an output current signal proportional to P.sub.1 -Q.sub.1. Signals P.sub.1, Q.sub.1 are, as will be described below, produced by shifting the voltage levels of demodulated signals P, Q, respectively, by the same amount, and further by reversing the phase of signal Q.sub.1. Thus P.sub.1 -Q.sub.1 =P+Q. Accordingly, differential amplifier (Q17, Q18; Q19, Q20) corresponds to adding circuit 162 shown in FIGS. 1 and 3. Similarly, differential amplifier (Q21, Q22; Q23, Q24), receiving signals P.sub.2 and Q.sub.2, provides an output current signal proportional to P.sup.2 -Q.sup.2. Since signals P.sub.2, Q.sub.2 are also provided by shifting demodulated signals P, Q by the same amount, P.sup.2 -Q.sup.2 =P-Q. Thus differential amplifier (Q21, Q22; Q23, Q24) corresponds to subtracting circuit 163 shown in FIGS. 1 and 3. The connection between the cross-coupled collectors of differential amplifier (Q17, Q18; Q19, Q20) and the coupled emitters of differential amplifier (Q21, Q22; Q23, Q24) constructs a quadratic multiplier for (P+Q)(P-Q). Thus this connection corresponds to multiplying circuit 164 shown in FIG. 1 and to multiplying operator 164 shown in FIG. 3. Similarly, the connection between differential amplifiers (Q13, Q14; Q15, Q16) and (Q17, Q18; Q19, Q20) corresponds to multiplying circuit 165 shown in FIG. 1 and to multiplying operator 165 shown in FIG. 3. In this way, serially connected four-stage differential amplifiers (Q11, Q12), (Q13, Q14; Q15, Q16), (Q17, Q18; Q19, Q20) and (Q21, Q22; Q23, Q24) constitute a biquadratic multiplier for computing P.times.Q.times.(P+Q).times.(P-Q).
The second part of the phase-error detecting circuit shown in FIG. 2 is made up of level-shifting circuits for shifting voltage levels of demodulated signals P, Q to the levels necessary to drive the bases of the differential amplifier arranged in each stage of the biquadratic multiplier. Differential amplifier (Q1, Q2) with load transistor Q7 is directed to shifting the voltage level of demodulated signal P to provide the base operating voltage for differential amplifier (Q17, Q18; Q19, Q20). This level-shifting circuit provides signal P.sub.1 in phase with demodulated signal P. Differential amplifier (Q5, Q6) with load transistor Q8 is directed to shifting the voltage level of demodulated signal Q to provide the base operating voltage for differential amplifier (Q17, Q18; Q19, Q20). This level-shifting circuit provides signal Q.sub.1 in reverse phase to demodulating signal Q. In order to ensure the same voltage shift, load transistors Q7 and Q8 are applied with the same base potential. Similarly, differential amplifier (Q3, Q4) with load transistor Q9, and differential amplifier (Q5, Q6) with load transistor Q10 provide base operating voltage signals P.sub.2, Q.sub.2 for differential amplifier (Q21, Q22; Q23, Q24), both signals P.sub.2 and Q.sub.2 being in phase with demodulated signals P, Q, respectively. A computation carried out by the biquadratic multiplier is supplied to the bases of transistors Q25, Q26 in order to be level-shifted and supplied to VCO 19 through LPF 18 (c.f. FIG. 1).
A problem encountered in the phase-error detecting circuit described above is that, since the biquadratic multiplier made up of serially connected four-stage differential amplifiers is used for computing phase error R, it is difficult to use such a phase-error detecting circuit in an IC fabricated by the silicon processing normally operated by a low-voltage power source such as 5 volts, because such a low-voltage power source is incapable of supplying a sufficient operating voltage to all the stages of the serially connected differential amplifiers. As a result, the QDPSK demodulating circuit according to the Costas loop method has been difficult to operate together with peripheral circuits under a single low-voltage power source, which is at variance with recent growing demand both for the PSK transmission of digitalized informations and for making devices small-sized and portable.